Hybrid Automatic Repeat Request Combiner and Method for Storing Hybrid Automatic Repeat Request Data

ABSTRACT

The invention provides a method for storing hybrid automatic repeat request (HARQ) data, the method including: when receiving new data of a coded block, a HARQ processor writing the new data into a high rate buffer memory (Cache) and a channel decoder; the Cache writing the new data into a data memory of the Cache or an external memory; and when receiving retransmitted data of the coded block, the HARQ processor obtaining a previous data corresponding to the retransmitted data from the data memory of the Cache or the external memory through the Cache, combining the retransmitted data and the previous data, and writing the combined data to the Cache and the channel decoder; the Cache writing the combined data into the data memory of the Cache or the external memory. The invention also provides a HARQ combiner.

TECHNICAL FIELD

The present invention relates to the hybrid automatic repeat request(HARQ) technology used in modern communication technology, such as3G/high speed downlink packet access (HSDPA), long time evolution (LTE)and world interoperability for microwave access (WiMax), and especiallyto a HARQ combiner and a method for storing HARQ data.

BACKGROUND OF THE RELATED ART

Wireless telecommunication technology, such as HSDPA, begins to usehybrid automatic repeat request (HARQ) technology. Due to presence ofinterference and fading of a wireless channel, when the receivedinformation after decoding has an error (for example a cyclic redundancycheck (CRC) check has an error), the receiving end may ask the sendingend to retransmit the information to the receiving end, and theretransmitted information may be the same with or different from theoriginal information. The receiving end can combine the informationreceived last time and the information currently retransmitted foranalysis so as to obtain correct information. Since the originalinformation needs to be retained to be combined with the retransmittedinformation of the next time, this information needs to be stored by amemory.

The receiving end needs to use a memory to store all error informationpackets, which are placed in a HARQ soft bit buffer or a HARQ memory.For a HSDPA with a low data velocity, such a memory used to store theHARQ information is small and may be implemented by a static randomaccess memory (SRAM). When high speed data and several HARQ processesexist, sometimes such a memory is considerably big. For LTE technology,data velocity is very high, for example Category 3, whose data velocityis 50 Mbps for upstream and 100 Mbps for downstream, and whose totalsoft bit number for downstream is 1237248 (as shown in Table 1). If 8bits are used to represent one soft bit, a 1.2 Mbyte memory is needed tosupport Category 3. Such a big memory (SRAM) used on the chip willincrease chip area and thus cause lack of competitiveness.

TABLE 1 Downlink physical layer parameter values set by UE CategoryMaximum Maximum Maximum number of number number of bits Total supportedof DL-SCH of a DL-SCH number layers transport block transport block ofsoft for spatial UE bits received received channel multiplexing Categorywithin a TTI within a TTI bits in DL Category 1 10296 10296 250368 1Category 2 51024 51024 1237248 2 Category 3 102048 75376 1237248 2Category 4 150752 75376 1827072 2 Category 5 302752 151376 3667200 4

To reduce chip area, the HARQ memory can be implemented by an off-chipdouble data rate (DDR)/double data rate synchronous dynamic randomaccess memory (SDRAM). However, the implementation of the off-chip SDRAMtakes up large bandwidth of DDR/SDRAM, and furthermore, the largequantity of accesses of the off-chip memory will directly increase thepower consumption of the chip. So, the existing HARQ memory needs to beimproved urgently.

SUMMARY OF THE INVENTION

The technical problem to solve by the invention is to provide a HARQcombiner and a method for storing HARQ data to reduce the area and powerconsumption of a base band chip.

To solve the above problem, the invention provides a method for storingHARQ data, the method comprising:

when receiving new data of a coded block, a HARQ processor writing thenew data into a Cache and a channel decoder; the Cache writing the newdata into a data memory of the Cache or into an external memory; and

when receiving retransmitted data of the coded block, the HARQ processorobtaining previous data corresponding to the retransmitted data from thedata memory of the Cache or the external memory through the Cache,combining the retransmitted data and the previous data, and writing thecombined data into the Cache and the channel decoder; the Cache writingthe combined data into the data memory of the Cache or the externalmemory.

The above method may be further characterized in that, the data memorycomprises one or more Cache lines;

the step of the Cache writing the new data or the combined data into thedata memory of the Cache comprises: writing the new data or the combineddata into a Cache line of the data memory, and recording a tag of theCache line in a tag memory, the tag being a high address of the new dataor the combined data stored in the Cache line;

prior to said step of when receiving retransmitted data of the codedblock, the HARQ processor obtaining previous data corresponding to theretransmitted data, the method further comprises: sending a controlsignal of reading the previous data to the Cache; when receiving thecontrol signal of reading the previous data, the Cache searching the tagmemory to determine whether a tag identical with the high address of theretransmitted data exists, if yes, the previous data being stored in theCache line corresponding to the tag, and the Cache reading the previousdata from the Cache line to the HARQ processor; or else, the previousdata not being stored in the data memory of the Cache, and the Cachereading the previous data in the external memory to a buffer in theCache, and then to the HARQ processor.

The above method may be further characterized in that, if the previousdata are not stored in the data memory of the Cache, after the previousdata are read from the external memory to the buffer, the method furthercomprises: writing the previous data into the Cache in following way:

searching the Cache, searching the tag memory to determine whether a tagidentical with the high address of the previous data exists:

if yes, writing the previous data into the Cache line corresponding tothe tag;

if not, assigning a Cache line to the previous data, and performingCache line replacement in following way:

if there is no data in the assigned Cache line, writing the previousdata directly to the assigned Cache line, and recording the tag of theCache line in the tag memory;

if there are data in the assigned Cache line, and CRC of the data iscorrect, then using the previous data to replace the data in the Cacheline, updating the tag of the Cache line, and writing the updated taginto the tag register;

if there are data in the assigned Cache line, and CRC of the data iswrong, then proceeding to step (a): storing the data into the externalmemory, storing the previous data into the assigned Cache line, andupdating the tag of the Cache line, writing the updated tag into the tagregister; or step (b): retaining the data in the assigned Cache line.

The above method may be further characterized in that, the step of theCache writing the new data or the combined data into the data memory ofthe Cache or the external memory comprises:

for the combined data, if the previous data to be combined are in theCache, writing the combined data into the Cache line in which theprevious data are stored;

for the new data or the combined data obtained when the previous data tobe combined are not in the Cache, the writing step comprises:

searching the tag memory to determine whether a tag identical with thehigh address of the new data or the combined data exists:

if yes, writing the new data or the combined data into the Cache linecorresponding to the tag;

if not, assigning a Cache line to the new data or the combined data,performing Cache line replacement according to a preset replacementprinciple, writing the new data or the combined data into the assignedCache line, or, to the external memory.

The above method may be further characterized in that, the step ofperforming Cache line replacement according to a preset replacementprinciple comprises:

if there is no data in the assigned Cache line, writing the new data orthe combined data directly into the assigned Cache line, and recordingthe tag of the Cache line in the tag memory;

if there are data in the assigned Cache line, and CRC of the data iscorrect, then using the new data or the combined data to replace thedata in the Cache line, updating the tag of the Cache line, and writingthe updated tag into the tag register;

if there are data in the assigned Cache line, and CRC of the data iswrong, then proceeding to step (a): storing the data into the externalmemory, storing the new data or the combined data into the assignedCache line, updating the tag of the Cache line, and writing the updatedtag into the tag register; or step (b): storing the new data or thecombined data into the external memory.

The above method may be further characterized in that, before the stepof performing the Cache line replacement, the method further comprises:setting a Cache line replacement identifier for indicating whether toperform replacement;

when performing the Cache line replacement, if there are data in theassigned Cache line, and the CRC of the data is wrong, then proceedingto the step (a) when the Cache line replacement identifier indicates toperform replacement; or else, proceeding to the step (b).

The above method may be further characterized in that, when the HARQprocessor writes the new data or the combined data of the coded blockinto the channel decoder, the method further comprises:

writing second tag information of the new data or the combined data ofthe coded block to the channel decoder, the second tag information ofthe new data or the combined data of the same coded block beingidentical;

the Cache receiving a CRC check result of the new data or the combineddata of the coded block and the second tag information thereof from thechannel decoder, and searching for a corresponding CRC check resultaccording to the second tag information of the data that has been storedin the Cache line when performing the Cache line replacement.

The above method may be further characterized in that, the HARQprocessor further receives the CRC check result of the coded block fromthe channel decoder and stores the CRC check result;

before the step of the HARQ obtaining the previous data of the codedblock, the method further comprises: when receiving the retransmitteddata of the coded block, checking the stored CRC check result of thecoded block, and skipping the coded block when the CRC check result ofthe coded block indicates that the CRC is correct; obtaining theprevious data of the coded block and performing combination processingonly when the CRC check result of the coded block indicates that the CRCis wrong.

The invention also provides a HARQ combiner, comprising a HARQ processorand a Cache, the Cache comprising a data memory, wherein:

the HARQ processor is configured to: when receiving new data of a codedblock, write the new data into the Cache and a channel decoder; whenreceiving retransmitted data of the coded block, obtain previous datacorresponding to the retransmitted data from a data memory of the Cacheor an external memory through the Cache, combine the retransmitted dataand the previous data, and write the combined data into the Cache andthe channel decoder;

the Cache is configured to: write the new data into the data memory ofthe Cache or to the external memory; return the previous data to theHARQ processor, and write the combined data into the data memory of theCache or to the external memory.

The above combiner may be further characterized in that, the Cachefurther comprises a Cache controller, a tag memory, a tag comparator,and the data memory comprises one or more Cache lines;

the HARQ processor is further configured to: when receiving theretransmitted data of the coded block, send a control signal of readingthe previous data to the Cache;

the Cache controller is configured to: write the new data or thecombined data into a Cache line of the data memory, record a tag of theCache line in a tag memory, the tag being a high address of the new dataor the combined data stored in the Cache line; when receiving thecontrol signal of reading the previous data, instruct the tag comparatorto search and obtain a search result, and read the previous data fromthe Cache line corresponding to the tag searched out to the HARQprocessor if the previous data of the retransmitted data are stored inthe data memory of the Cache; or else, read the previous data in theexternal memory into a buffer in the Cache, and then to the HARQprocessor;

the tag memory is configured to: search the tag memory to determinewhether a tag identical with the high address of the retransmitted dataexists according to an instruction of the Cache controller, if yes, theprevious data are stored in the Cache line corresponding to the tag, orelse, the previous data are not in the data memory of the Cache.

The above combiner may be further characterized in that, the Cachecontroller is further configured to: when the previous data are notstored in the data memory of the Cache, after reading the previous datafrom the external memory to the buffer, further write the previous datainto the Cache in following way:

instructing the tag comparator to search and obtain a search result,writing the previous data to an assigned Cache line if a tag identicalwith the high address of the previous data exists in the tag memory;

if not, assigning a Cache line to the previous data, and performingCache line replacement in following way:

if there is no data in the assigned Cache line, writing the previousdata directly to the assigned Cache line, and recording the tag of theCache line in the tag memory;

if there are data in the assigned Cache line, and CRC of the data iscorrect, then using the previous data to replace the data in the Cacheline, updating the tag of the Cache line, and writing the updated taginto the tag register;

if there are data in the assigned Cache line, and CRC of the data iswrong, then proceeding to (a): storing the data into the externalmemory, storing the previous data into the assigned Cache line, updatingthe tag of the Cache line, and writing the updated tag into the tagregister; or (b): retaining the data in the assigned Cache line;

the tag memory is configured to: search the tag memory to determinewhether a tag identical with the high address of the previous dataexists according to the instruction of the Cache controller, and returnthe search result to the Cache controller.

The above combiner may be further characterized in that, the Cachecontroller is further configured to: when the previous data to becombined are in the Cache, write the combined data to the Cache line inwhich the previous data are stored; for the new data or the combineddata obtained when the previous data to be combined are not in theCache, write in following way:

instructing the tag comparator to search and obtain the search result asto whether a tag identical with the high address of the new data or thecombined data exists in the tag memory:

if yes, writing the new data or the combined data into the Cache linecorresponding to the tag;

if not, assigning a Cache line to the new data or the combined data,performing Cache line replacement according to a preset replacementprinciple, and writing the new data or the combined data into theassigned Cache line, or, to the external memory;

the tag comparator is configured to: search the tag memory to determinewhether a tag identical with the high address of the new data or thecombined data exists in according to the instruction of the Cachecontroller, and return the search result to the Cache controller.

The above combiner may be further characterized in that, the Cachecontroller being configured to: perform the Cache line replacementaccording to a preset replacement principle in following way:

if there is no data in the assigned Cache line, writing the new data orthe combined data directly into the assigned Cache line, and recordingthe tag of the Cache line in the tag memory;

if there are data in the assigned Cache line, and CRC of the data iscorrect, then using the new data or the combined data to replace thedata in the Cache line, updating the tag of the Cache line, and writingthe updated tag into the tag register;

if there are data in the assigned Cache line, and CRC of the data iswrong, then proceeding to (a): storing the data in the external memory,storing the new data or the combined data into the assigned Cache line,updating the tag of the Cache line, and writing the updated tag into thetag register; or proceeding to (b): storing the new data or the combineddata into the external memory.

The above combiner may be further characterized in that, a Cache linereplacement identifier is set in the Cache to indicate whether toperform replacement;

the Cache controller is further configured to: when performing the Cacheline replacement, if there are data in the assigned Cache line, and theCRC of the data is wrong, then proceed to the (a) when the Cache linereplacement identifier indicates to perform replacement; or else,proceed to the (b).

The above combiner may be further characterized in that, the HARQprocessor is further configured to: when writing the new data or thecombined data of the coded block into the channel decoder, write secondtag information of the new data or the combined data of the coded blockinto the channel decoder, the second tag information of the new data orthe combined data of the same coded block being identical;

the Cache controller is further configured to: receive the CRC checkresult of the new data or the combined data of the coded block and thesecond tag information thereof from the channel decoder, and search fora corresponding CRC check result according to the second tag informationof the data that has been stored in the Cache line when performing theCache line replacement.

The above combiner may be further characterized in that, the HARQprocessor is further configured to: receive the CRC check result of thecoded block from the channel decode and store the CRC check result; whenreceiving the retransmitted data of the coded block, check the storedCRC check result of the coded block, and skip the coded block when theCRC check result of the coded block indicates that the CRC is correct;obtain the previous data of the coded block and perform combinationprocessing only when the CRC check result of the coded block indicatesthat the CRC is wrong.

The invention provides a HARQ combiner having a Cache and a method forHARQ data storage. The invention is very beneficial in reducing the chiparea and power consumption and improving the competitiveness. The methodwill be of great strategic significance at present and in the futurewhen the communication technology with increasing data rate developscontinuously day by day.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a general architecture of a SOC base band chip of a multi-coreprocessor;

FIG. 2 describes an architecture diagram of a HARQ combiner having aCache;

FIG. 3 describes an architecture diagram of the HARQ Cache;

FIG. 4 further describes the processing of the retransmitted data by thecontrol logic in the invention;

FIG. 5 is a diagram of the division of the physical addresses of CBblocks of the HARQ;

FIG. 6 is a diagram of a CB block of the HARQ in the Cache RAM;

FIG. 7 is a diagram of setting the TAG CRC status bits.

PREFERRED EMBODIMENTS OF THE PRESENT INVENTION

The invention introduces a Cache into a HARQ combiner to provide amethod for implementing a hierarchy memory having its own Cache for theHARQ processing in a wireless communication system. The area and powerconsumption of a wireless base band chip are reduced by replacing theon-chip SRAM with the Cache and using the method of hierarchy storage ofthe off-chip DDR/SDRAM.

To utilize the low cost and high efficiency of the on-chip Cache and thelarge volume and low cost of the off-chip DDR/SDRAM, the inventionprovides an implementation method for dynamic assignment of a HARQmemory having a Cache. The Cache may be used to store, according to theselection of the storage space size of the on-chip Cache, part of codedblocks, one or more coded blocks, and soft bit data of one or more HARQprocesses, and may be updated dynamically. The Cache may be a directmapped, or a set-associative.

The HARQ combiner provided by the invention comprises a HARQ processorand a Cache, wherein:

when receiving new data, a HARQ processor writes the new data into theCache, and simultaneously into a transmission channel decoder (such asTurbo, CRC and so on, which can be outside the HARQ combiner);

when receiving a retransmitted data, the HARQ processor combines the newdata and the previous data stored in the Cache, and write the combineddata into the Cache, and simultaneously into the transmission channeldecoder.

When sending a data packet to a channel decoder, the HARQ processorsimultaneously transmits the high address, i.e. the tag (CRC_Tag,process number and CB block number, as show in FIG. 7), of the CB blockof the HRAQ process corresponding to the data packet to the channeldecoder.

When feeding back the CRC result of the CB block to the Cachecontroller, the transmission channel decoder sends simultaneously theCRC_Tag corresponding to the CB block to the Cache controller. The Cachecontroller determines, using the CRC_Tag and the CRC result, whether thecontent of the Cache is replaced during the assignment of the new Cacheline. Based on the existing random replacement algorithm and the leastrecently used replacement algorithm (LRU) and other replacementalgorithms of the Cache, the invention provides a new replacementalgorithm using the CRC result and the transmitted CRC_Tag. In view ofthe simplification of the design, the “write buffer” of the Cache maydirectly assign the Cache line with no need of reading the possiblyuncompleted data in the line from the external, thus reducing the powerconsumption and area. When the data of one CB block does not take upfully its last Cache line, the deficiency is that part of a Cache linein the Cache (part of data of one Cache line for each CB block at most)is not used, but no error will occurs. This is a design balance, and ifit is necessary to use the space of the Cache line sufficiently, the“write allocated buffer” needs to synthesize the data from the HARQcombiner and the external memory.

The invention performs processing based on the coded block (CB), and theprocessing of the transmission block composed of a plurality of codedblocks involves processing of each coded block followed by overallprocessing (such as CTC check of the transmitting block) of thetransmitting block.

Although the CB blocks are the basis in the description of theinvention, due the use of the Cache Tag and the CRC result directlymapped to the CRC_Tag, such a HARQ_Cache is also suitable for theprocessing mode for any data which do not take the CB block as a unit.

The invention comprises a coded block CRC status register(CB_CRC_Statu_Reg), and each coded block corresponds to a CRC statusidentifier for indicating the CRC status of the coded block. Wherein,the CRC status identifier of a coded block in the coded block CRC statusregister is set according to the CRC result of the codec block. Thevalues of the CRC status identifier can be set in the following way:when the CRC status identifier is 1, it indicates the CRC of the codedblock is wrong; when the CRC status identifier is 0, it indicates theCRC of the coded block is correct. Of course, 0 can be used to indicatethe CRC of the coded block is wrong, and 1 indicates the CRC of thecoded block is correct. The invention is not limited thereto. The HARQcombiner may control data processing during the retransmission accordingto the CRC status identifier. When receiving the retransmitted data, theHARQ combiner may not process the coded block whose corresponding CRCstatus identifier indicates that CRC is correct (for example, CRC statusidentifier is 0), thus saving power consumption, and it processesnormally the code block whose corresponding CRC status identifierindicates CRC error (for example, CRC status identifier is 1).

The invention provides a HARQ combiner, comprising a HARQ processor anda Cache, the Cache comprising a data memory, wherein:

the HARQ processor is used to, when receiving new data of a coded block,write the new data into the Cache and a channel decoder; when receivingretransmitted data of the coded block, obtain previous datacorresponding to the retransmitted data from a data memory of the Cacheor an external memory through the Cache, combine the retransmitted dataand the previous data, and write the combined data into the Cache andthe channel decoder;

the Cache is used to write the new data to the data memory of the Cacheor to the external memory; return the previous data to the HARQprocessor, and write the combined data into the data memory of the Cacheor to the external memory.

Wherein, the HARQ processor is used to, when receiving the retransmitteddata of the coded block, send a control signal of reading the previousdata to the Cache;

the Cache controller is used to write the new data or the combined datainto a Cache line of the data memory, and record a tag of the Cache linein a tag memory, the tag being a high address of the new data or thecombined data stored in the Cache line; it is further used to, whenreceiving the control signal of reading the previous data, instruct thetag comparator to search and obtain the search result, read the previousdata from the Cache line corresponding to the searched tag to the HARQprocessor if the previous data of the retransmitted data are stored inthe data memory of the Cache; or else, read the previous data in theexternal memory to a buffer in the Cache, and then to the HARQprocessor;

the tag memory is used to search the tag memory to determine whether atag identical with the high address of the retransmitted data existsaccording to the instruction of the Cache controller; if yes, theprevious data are stored in the Cache line corresponding to the tag, orelse, the previous data are not stored in the data memory of the Cache.

Wherein, the Cache controller is further used to, when the previous dataare not stored in the data memory of the Cache, after reading theprevious data from the external memory to the buffer, further write theprevious data into the Cache in following way:

instructing the tag comparator to search and obtain the search result,writing the previous data into an assigned Cache line if a tag identicalwith the high address of the previous data exists in the tag memory;

if not, assigning a Cache line to the previous data, performing Cacheline replacement in following way:

if there is no data in the assigned Cache line, writing the previousdata directly into the assigned Cache line, and recording the tag of theCache line in the tag memory;

if there are data in the assigned Cache line, and CRC of the data iscorrect, then using the previous data to replace the data in the Cacheline, updating the tag of the Cache line, and writing the updated tag inthe tag register;

if there are data in the assigned Cache line, and CRC of the data iswrong, then proceeding to (a): storing the data in the external memory,storing the previous data in the assigned Cache line, updating the tagof the Cache line, and writing the updated tag in the tag register; or(b): retaining the data in the assigned Cache line;

the tag memory is used to search the tag memory to determine whether atag identical with the high address of the previous data existsaccording to the instruction of the Cache controller, and return thesearch result to the Cache controller.

Wherein, the Cache controller is used to, when the previous data to becombined are in the Cache, write the combined data into the Cache linein which the previous data are stored; for the new data or the combineddata obtained when the previous data to be combined are not in theCache, write in following way:

instructing the tag comparator to search and obtain the search result,whether a tag identical with the high address of the new data or thecombined data exists in the tag memory:

if yes, writing the new data or the combined data into the Cache linecorresponding to the tag;

if not, assigning a Cache line to the new data or the combined data,performing Cache line replacement according to a preset replacementprinciple, and writing the new data or the combined data to the assignedCache line, or, to the external memory;

the tag comparator is configured to: search the tag memory to determinewhether a tag identical with the high address of the new data or thecombined data exists according to the instruction of the Cachecontroller, and return the search result to the Cache controller.

Wherein, the Cache controller is used to perform the Cache linereplacement according to a preset replacement principle in the followingway:

if there is no data in the assigned Cache line, writing the new data orthe combined data directly into the assigned Cache line, and recordingthe tag of the Cache line in the tag memory;

if there are data in the assigned Cache line, and CRC of the data iscorrect, then using the new data or the combined data to replace thedata in the Cache line, updating the tag of the Cache line, and writingthe updated tag into the tag register;

if there are data in the assigned Cache line, and CRC of the data iswrong, then proceed to (a): storing the data in the external memory,storing the new data or the combined data in the assigned Cache line,updating the tag of the Cache line, and writing the updated tag in thetag register; or proceeding to (b): storing the new data or the combineddata in the external memory.

Wherein, a Cache line replacement identifier is set in the Cache toindicate whether to perform replacement;

the Cache controller is used to, when performing the Cache linereplacement, if there are data in the assigned Cache line, and the CRCof the data is wrong, proceed to the (a) when the Cache line replacementidentifier indicates to perform replacement; or else, proceed to the(b).

Wherein, the HARQ processor is further configured to, when writing thenew data or the combined data of the coded block into the channeldecoder, write second tag information of the new data or the combineddata of the coded block into the channel decoder, the second taginformation of the new data or the combined data of the same coded blockbeing identical;

the Cache controller is further used to receive the CRC check result ofthe new data or the combined data of the coded block and the second taginformation thereof from the channel decoder, and search for acorresponding CRC check result according to the second tag informationof the data that has been stored in the Cache line when performing theCache line replacement.

Wherein, the HARQ processor is further used to receive the CRC checkresult of the coded block from the channel decode and store the CRCcheck result; when receiving the retransmitted data of the coded block,check the stored CRC check result of the coded block, and skip the codedblock when the CRC check result of the coded block indicates that theCRC is correct; obtain the previous data of the coded block and make acombination processing only when the CRC check result of the coded blockindicates that the CRC is wrong.

The invention also provides a method for storing a HARQ data, the methodcomprising:

when receiving new data of a coded block, a HARQ processor writing thenew data Cache into a Cache and a channel decoder; the Cache writing thenew data into a data memory of the Cache or into an external memory;

when receiving retransmitted data of the coded block, the HARQ processorobtaining previous data corresponding to the retransmitted data from thedata memory of the Cache or the external memory through the Cache,combining the retransmitted data and the previous data, writing thecombined data into the Cache and the channel decoder; the Cache writingthe combined data into the data memory of the Cache or into the externalmemory.

The data memory comprises one or more Cache lines;

the step of the Cache writing the new data or the combined data into thedata memory of the Cache comprises: writing the new data or the combineddata into a Cache line of the data memory, and recording a tag of theCache line in a tag memory, the tag being a high address of the new dataor the combined data stored in the Cache line;

when receiving the retransmitted data of the coded block, the HARQprocessor sending a control signal of reading the previous data to theCache; when receiving the control signal of reading the previous data,the Cache searching the tag memory to determine whether a tag identicalwith the high address of the retransmitted data exists, if yes, theprevious data being stored in the Cache line corresponding to the tag,the Cache reading the previous data from the Cache line to the HARQprocessor; or else, the previous data being not stored in the datamemory of the Cache, the Cache reading the previous data in the externalmemory to a buffer in the Cache, and then to the HARQ processor.

Wherein, if the previous data are not stored in the data memory of theCache, after the previous data are read from the external memory to thebuffer, the method further comprises writing the previous data into theCache in following way:

searching the Cache, searching the tag memory to determine whether a tagidentical with the high address of the previous data exists:

if yes, writing the previous data into the Cache line corresponding tothe tag;

if not, assigning a Cache line to the previous data, performing Cacheline replacement in following way:

if there is no data in the assigned Cache line, writing the previousdata directly into the assigned Cache line, and recording the tag of theCache line in the tag memory;

if there are data in the assigned Cache line, and CRC of the data iscorrect, then using the previous data to replace the data in the Cacheline, updating the tag of the Cache line, and writing the updated taginto the tag register;

if there are data in the assigned Cache line, and CRC of the data iswrong, then proceeding to step (a): storing the data in the externalmemory, storing the previous data in the assigned Cache line, updatingthe tag of the Cache line, and writing the updated tag in the tagregister; or step (b): retaining the data in the assigned Cache line.

Wherein, the Cache writes the new data or the combined data into thedata memory of the Cache or the external memory in the following way:

for the combined data, if the previous data to be combined are in theCache, writing the combined data into the Cache line in which theprevious data are stored;

for the new data or the combined data obtained when the previous data tobe combined are not in the Cache, writing in the following way:

searching the tag memory to determine whether a tag identical with thehigh address of the new data or the combined data exists:

if yes, writing the new data or the combined data into the Cache linecorresponding to the tag;

if not, assigning a Cache line to the new data or the combined data,performing Cache line replacement according to a preset replacementprinciple, writing the new data or the combined data into the assignedCache line, or, to the external memory.

Wherein, the step of performing Cache line replacement according to apreset replacement principle comprises:

if there is no data in the assigned Cache line, writing the new data orthe combined data directly into the assigned Cache line, and recordingthe tag of the Cache line in the tag memory;

if there are data in the assigned Cache line, and CRC of the data iscorrect, then using the new data or the combined data to replace thedata in the Cache line, updating the tag of the Cache line, and writingthe updated tag into the tag register;

if there are data in the assigned Cache line, and CRC of the data iswrong, then proceeding to step (a): storing the data in the externalmemory, storing the new data or the combined data in the assigned Cacheline, updating the tag of the Cache line, and writing the updated taginto the tag register; or step (b): storing the new data or the combineddata in the external memory.

Wherein, a Cache line replacement identifier is further configured toindicate whether to perform replacement; when performing the Cache linereplacement, if there are data in the assigned Cache line, and the CRCof the data is wrong, then proceed to the step (a) when the Cache linereplacement identifier indicates to perform replacement; or else,proceed to the step (b).

Wherein, when writing the new data or the combined data of the codedblock to the channel decoder, the HARQ processor writes second taginformation of the new data or the combined data of the coded block intothe channel decoder, the second tag information of the new data or thecombined data of the same coded block being identical;

the Cache receives the CRC check result of the new data or the combineddata of the coded block and the second tag information thereof from thechannel decoder, and searches for a corresponding CRC check resultaccording to the second tag information of the data that has been storedin the Cache line when performing the Cache line replacement.

Wherein, the HARQ processor further receives the CRC check result of thecoded block from the channel decoder and stores the CRC check result;when receiving the retransmitted data of the coded block, the HARQprocessor checks the stored CRC check result of the coded block, andskips the coded block when the CRC check result of the coded blockindicates that the CRC is correct; obtains the previous data of thecoded block and makes a combination processing only when the CRC checkresult of the coded block indicates that the CRC is wrong.

FIG. 1 is a general architecture of a system on chip (SOC) base bandchip of a multi-core processor. In this specific instance, the SOC baseband chip comprises a digital signal processor (DSP) and a CPU (such asan ARM processor), a DMA (direct memory access), peripherals, a modemaccelerator, and a channel decoder (Turbo, CRC and so on). HARQ is partof a modem accelerator and may be a bus controller. SRAM is an on-chipmemory. The HARQ combiner is placed at the location of the SOC, whichenables the HARQ combiner to use the on-chip Cache, on-chip SRAM and theoff-chip DDR/SDRAM. When reading the data in the Cache, if the data arenot in the Cache, i.e. Cache Miss, the linefill buffer of the Cache mayread the data of the SRAM, DDR/SDRAM into the HARQ combiner.

FIG. 2 describes an architecture diagram of the HARQ combiner having aCache. It can be seen from the diagram that the received data, hereinreferred to I, Q data received from the radio frequency, passes throughADC (digital-analog conversion), filtering, and forward processing, suchas channel estimation, MIMO, balancer, and so on, and then generate aLLR (log likelihood ratio) soft bit, which is stored in a buffer. Theoverall controller of the HARQ combiner generates a control signal toread the soft bit data from the buffer according to the initial address,data block size and status (new data or retransmitted data) and so on ofa CB block and the current process.

Wherein, the HARQ combiner comprises a HARQ processor and a Cache,wherein, the HARQ processor comprises a HARQ controller and a datacombination processing unit.

If the data are new data, the data may be written into the input bufferof a channel decoder (such as Turbo), and simultaneously written intothe Cache. The Cache can be set to use the Cache line write assigningpolicy, and in the case of Cache Miss, one piece of Cache line isassigned to the data, and the value of high address (CB_Tag) isrecorded. For the purpose of parallel operation, the size of theoperated data may be one Cache line. While the length of the Cache linemay be the length of one DDR concurrency (burst). In the case of Cachehit, the data will be written into the Cache, wherein, the tagcomparator compares the CB_TAG in the tag register with the CB_TAB ofthe new data, and if a CB_TAG the same with the CB_TAG of the new dataexists in the tag register, then Cache is hit, or else, Cache is missed.

If the data are a retransmitted data, the retransmitted data needs to becombined with the previous data. The HARQ controller checks whether theprevious data are in the Cache according to the current process and theaddress of the CB block. If the previous data are in the Cache, Cachehit is generated, and the previous data (or the whole Cache line) isread out into a data combination processing unit to be combined with theretransmitted data. If the previous data are not in the Cache (Cachemiss), the Cache controller will generate a line fill command to readthe content in the external memories into the Cache and simultaneouslysend to the data combination processing unit to perform the combinationof the retransmitted data and the previous data. The combined data aretransmitted back to the Cache and the input buffer of the channeldecoder (such as Turbo).

The CB block data are all written into the input buffer of the channeldecoder (such as Turbo), and simultaneously the high address of the CBblock (CB_Tag) is written into the channel decoder.

After all the data of a CB block are written into the input buffer ofthe channel decoder (such as Turbo), the channel decoder and a CRCchecker are initiated. The channel decoder feeds back the CRC result tothe HARQ processor, and simultaneously sends the corresponding CRC_Tagto the Cache controller.

FIG. 3 describes an architecture diagram of the HARQ Cache. It can beseen from the diagram that the HARQ Cache comprises:

read and write interfaces, such as the control signal, address signaland data signal, connected to the HARQ processor; it also comprises abus interface for the access of the external memories that is used toconnect the bus of the SOC, such as the cross-bar bus;

a HARQ controller, used to control and coordinate the work of the Cache.

A HARQ Cache has at least three buffers, namely a write buffer, a lineread buffer and a line fill buffer respectively.

The write buffer receives the write data of the HARQ processor, andwrites the data into the Cache or the external memory.

The line read buffer reads a Cache line and sends to the HARQ processorfor combination in case of Cache hit.

The line fill buffer reads the content of the external memories andsends to the HARQ processor and the Cache line.

The HARQ Cache has two multiplexers to select different data streams.For example, the read data can be selected from the line read buffer orthe line fill buffer; the write data can be selected from the line readbuffer or the write buffer.

The HARQ Cache further has a tag comparator used for the tag comparisonof the Cache to determine whether the data are in the Cache.

The HARQ Cache further comprises a data memory (data RAM) to store data(Cache line), and a tag memory (Tag RAM) to store tag values.

The HARQ Cache further comprises a CRC interface. The channel decodersends the CRC result (CRC_PASS) and the corresponding CRC_TAG value backto the Cache controller, and these two groups of values will be used todetermine whether to replace a Cache line during the Cache replacementalgorithm.

FIG. 4 further describes the processing of the retransmitted data by thecontrol logic in the invention. For new data, each CB block needs to beprocessed; while for retransmitted data, the CB block having an originalcorrect CRC does not need to be processed. For retransmitted data, thecontroller checks the content (the content is transmitted by the channeldecoder) of the CRC status register (CB_CRC_Statu_Reg, which is the sameas the value of the CRC_PASS), and if the CRC status bit correspondingto the CB is 0, it suggests that the last CRC is correct and there is noneed for processing. If the CRC status bit corresponding to the CB is 1,it suggests that the last CRC is wrong and the CB block needs to beprocessed.

FIG. 5 illustrates the division of the physical addresses of CB blocksof the HARQ, wherein, the tag section will be stored in the tag RAM.Data are stored in the data RAM, and each row shown in the figure is aline. The physical address of the HARQ process CB block may be composedof a HARQ process number (process ID), a CB block number and a CB blocklength. The process number (process ID), the CB block number and the CBblock length compose a tag (CB_TAB in the figure). The tag comparatorcompares the tag value with the tag RAM to determine whether the Cacheis hit. If not, a Cache line may be assigned to the data that are nothit, and this tag is simultaneously written into the tag RAM for tagcomparison of the data of the next time. When the data from the sameaddress comes next time, a hit (Cache hit) will be generated.

FIG. 6 is a diagram of the CB block of the HARQ in the Cache RAM. Pleasenote that although the physical addresses of the CB blocks arecontinuous, they may be in different locations in the Cache and are justdrawn as continuous for convenience of explanation. It can be seen fromthe figure that one CB block may have one Cache line which is partlynull, i.e. not used sufficiently. However, such a division of CBaddresses may enable a CB to be able to provide the same high tag forsetting of tag CRC status bits.

FIG. 7 is a diagram of setting the tag CRC status bits. Since theprocess number of each HARQ plus the CB block number is unique (hereinreferred to as CRC_TAG), this section of information may be transmittedto the channel decoder. After the CRC result of the channel decoder isout, the CRC result of the CB block and the corresponding CRC_TAG valueare sent together back to the Cache controller. Inside the Cache thereare a group of storage components for recording the values of CRC_TAGand a CRC status register for recording whether corresponding CB blockspass the CRC (CRC_PASS), and these two groups of values are used todefine the replacement method of the Cache line.

The replacement method of the HARQ Cache line provided by the inventionwill be described below. Based on the “random” and the least recentlyused replacement algorithm (LRU) and other replacement algorithmscommonly used in the industry, the invention uses the result of CRC_PASSand the transmitted CRC_Tag to make a further improvement.

When a Cache is not hit (Cache Miss), after the replaced Cache line isfound by the selected random or LRU replacement algorithm, the CRC_Tagvalue is compared with the value corresponding to the tag, originally inthe tag RAM, of the Cache line:

if there is no identical value, the Cache line may be replaced;

if there is a value the same with the CRC_TAG, the value of the CRC_PASScorresponding to the CRC_TAG is checked:

a, if the value of the CRC_PASS is 0, it suggests that the CRC of the CBblock is correct, so the Cache line may be replaced:

b, if the value of the CRC_PASS is 1, it suggests that the CRC of the CBblock is wrong, and the CB block is to be combined with the next data. ACache_Line_Relpace register bit can be used to process flexibly:

if the Cache_Line_Relpace is set to be 1, the Cache line may bereplaced, although the content in the Cache line is to be used;

if the Cache_Line_Relpace is set to be 0, the Cache line can not bereplaced, so the current data can not be retained in the Cache, whichagain divides into two cases:

1) if it is a read Cache, the data read from the external memories aresent directly to the HARQ combiner, and this section of data will not beretained in the Cache;

2) if it is a write Cache, the data sent from the HARQ processor will besent directly to the external memories and not retained in the Cache.

The invention is suitable for the HARQ combiner comprising aprogrammable or un-programmable controlling component.

INDUSTRIAL APPLICABILITY

The invention provides a HARQ combiner having a Cache and a method forHARQ data storage. The invention is very beneficial in reducing the chiparea and power consumption and improving the competitiveness. The methodwill be of great strategic significance at present and in the futurewhen the communication technology with increasing data rate developscontinuously day by day.

1. A method for storing hybrid automatic repeat request (HARQ) data, themethod comprising: when receiving new data of a coded block, a HARQprocessor writing the new data into a high rate buffer memory (Cache)and a channel decoder; the Cache writing the new data into a data memoryof the Cache or into an external memory; and when receivingretransmitted data of the coded block, the HARQ processor obtainingprevious data corresponding to the retransmitted data from the datamemory of the Cache or the external memory through the Cache, combiningthe retransmitted data and the previous data, and writing the combineddata into the Cache and the channel decoder; the Cache writing thecombined data into the data memory of the Cache or the external memory.2. The method according to claim 1, wherein, the data memory comprisesone or more Cache lines; the step of the Cache writing the new data orthe combined data into the data memory of the Cache comprises: writingthe new data or the combined data into a Cache line of the data memory,and recording a tag of the Cache line in a tag memory, the tag being ahigh address of the new data or the combined data stored in the Cacheline; prior to when receiving retransmitted data of the coded block, theHARQ processor obtaining previous data corresponding to theretransmitted data, the method further comprises: sending a controlsignal of reading the previous data to the Cache; when receiving thecontrol signal of reading the previous data, the Cache searching the tagmemory to determine whether a tag identical with the high address of theretransmitted data exists, if yes, the previous data being stored in theCache line corresponding to the tag, and the Cache reading the previousdata from the Cache line to the HARQ processor; or else, the previousdata not being stored in the data memory of the Cache, and the Cachereading the previous data in the external memory to a buffer in theCache, and then to the HARQ processor.
 3. The method according to claim2, wherein, if the previous data are not stored in the data memory ofthe Cache, after the previous data are read from the external memory tothe buffer, the method further comprises: writing the previous data intothe Cache in following way: searching the Cache, searching the tagmemory to determine whether a tag identical with the high address of theprevious data exists: if yes, writing the previous data into the Cacheline corresponding to the tag; if not, assigning a Cache line to theprevious data, and performing Cache line replacement in following way:if there is no data in the assigned Cache line, writing the previousdata directly to the assigned Cache line, and recording the tag of theCache line in the tag memory; if there are data in the assigned Cacheline, and CRC of the data is correct, then using the previous data toreplace the data in the Cache line, updating the tag of the Cache line,and writing the updated tag into the tag register; if there are data inthe assigned Cache line, and CRC of the data is wrong, then proceedingto step (a): storing the data into the external memory, storing theprevious data into the assigned Cache line, and updating the tag of theCache line, writing the updated tag into the tag register; or step (b):retaining the data in the assigned Cache line.
 4. The method accordingto claim 2, wherein, the step of the Cache writing the new data or thecombined data into the data memory of the Cache or the external memorycomprises: for the combined data, if the previous data to be combinedare in the Cache, writing the combined data into the Cache line in whichthe previous data are stored; for the new data or the combined dataobtained when the previous data to be combined are not in the Cache, thewriting step comprises: searching the tag memory to determine whether atag identical with the high address of the new data or the combined dataexists: if yes, writing the new data or the combined data into the Cacheline corresponding to the tag; if not, assigning a Cache line to the newdata or the combined data, performing Cache line replacement accordingto a preset replacement principle, writing the new data or the combineddata into the assigned Cache line, or, to the external memory.
 5. Themethod according to claim 4, wherein, the step of performing Cache linereplacement according to a preset replacement principle comprises: ifthere is no data in the assigned Cache line, writing the new data or thecombined data directly into the assigned Cache line, and recording thetag of the Cache line in the tag memory; if there are data in theassigned Cache line, and CRC of the data is correct, then using the newdata or the combined data to replace the data in the Cache line,updating the tag of the Cache line, and writing the updated tag into thetag register; if there are data in the assigned Cache line, and CRC ofthe data is wrong, then proceeding to step (a): storing the data intothe external memory, storing the new data or the combined data into theassigned Cache line, updating the tag of the Cache line, and writing theupdated tag into the tag register; or step (b): storing the new data orthe combined data into the external memory.
 6. The method according toclaim 3, wherein, before the step of performing the Cache linereplacement, the method further comprises: setting a Cache linereplacement identifier for indicating whether to perform replacement;when performing the Cache line replacement, if there are data in theassigned Cache line, and the CRC of the data is wrong, then proceedingto the step (a) when the Cache line replacement identifier indicates toperform replacement; or else, proceeding to the step (b).
 7. The methodaccording to claim 3, wherein, when the HARQ processor writes the newdata or the combined data of the coded block into the channel decoder,the method further comprises: writing second tag information of the newdata or the combined data of the coded block to the channel decoder, thesecond tag information of the new data or the combined data of the samecoded block being identical; the Cache receiving a CRC check result ofthe new data or the combined data of the coded block and the second taginformation thereof from the channel decoder, and searching for acorresponding CRC check result according to the second tag informationof the data that has been stored in the Cache line when performing theCache line replacement.
 8. The method according to claim 1, the methodfurther comprising: the HARQ processor further receiving the CRC checkresult of the coded block from the channel decoder and storing the CRCcheck result; before the step of the HARQ obtaining the previous data ofthe coded block, the method further comprising: when receiving theretransmitted data of the coded block, checking the stored CRC checkresult of the coded block, and skipping the coded block when the CRCcheck result of the coded block indicates that the CRC is correct;obtaining the previous data of the coded block and performingcombination processing only when the CRC check result of the coded blockindicates that the CRC is wrong.
 9. A hybrid automatic repeat request(HARQ) combiner, comprising a HARQ processor and a high rate buffermemory (Cache), the Cache comprising a data memory, wherein: the HARQprocessor is configured to: when receiving new data of a coded block,write the new data into the Cache and a channel decoder; when receivingretransmitted data of the coded block, obtain previous datacorresponding to the retransmitted data from a data memory of the Cacheor an external memory through the Cache, combine the retransmitted dataand the previous data, and write the combined data into the Cache andthe channel decoder; the Cache is configured to: write the new data intothe data memory of the Cache or to the external memory; return theprevious data to the HARQ processor, and write the combined data intothe data memory of the Cache or to the external memory.
 10. The combineraccording to claim 9, wherein, the Cache further comprises a Cachecontroller, a tag memory, a tag comparator, and the data memorycomprises one or more Cache lines; the HARQ processor is furtherconfigured to: when receiving the retransmitted data of the coded block,send a control signal of reading the previous data to the Cache; theCache controller is configured to: write the new data or the combineddata into a Cache line of the data memory, record a tag of the Cacheline in a tag memory, the tag being a high address of the new data orthe combined data stored in the Cache line; when receiving the controlsignal of reading the previous data, instruct the tag comparator tosearch and obtain a search result, and read the previous data from theCache line corresponding to the tag searched out to the HARQ processorif the previous data of the retransmitted data are stored in the datamemory of the Cache; or else, read the previous data in the externalmemory into a buffer in the Cache, and then to the HARQ processor; thetag memory is configured to: search the tag memory to determine whethera tag identical with the high address of the retransmitted data existsaccording to an instruction of the Cache controller, if yes, theprevious data are stored in the Cache line corresponding to the tag, orelse, the previous data are not in the data memory of the Cache.
 11. Thecombiner according to claim 10, wherein, the Cache controller is furtherconfigured to: when the previous data are not stored in the data memoryof the Cache, after reading the previous data from the external memoryto the buffer, further write the previous data into the Cache infollowing way: instructing the tag comparator to search and obtain asearch result, writing the previous data to an assigned Cache line if atag identical with the high address of the previous data exists in thetag memory; if not, assigning a Cache line to the previous data, andperforming Cache line replacement in following way: if there is no datain the assigned Cache line, writing the previous data directly to theassigned Cache line, and recording the tag of the Cache line in the tagmemory; if there are data in the assigned Cache line, and CRC of thedata is correct, then using the previous data to replace the data in theCache line, updating the tag of the Cache line, and writing the updatedtag into the tag register; if there are data in the assigned Cache line,and CRC of the data is wrong, then proceeding to (a): storing the datainto the external memory, storing the previous data into the assignedCache line, updating the tag of the Cache line, and writing the updatedtag into the tag register; or (b): retaining the data in the assignedCache line; the tag memory is configured to: search the tag memory todetermine whether a tag identical with the high address of the previousdata exists according to the instruction of the Cache controller, andreturn the search result to the Cache controller.
 12. The combineraccording to claim 10, wherein, the Cache controller is furtherconfigured to: when the previous data to be combined are in the Cache,write the combined data to the Cache line in which the previous data arestored; for the new data or the combined data obtained when the previousdata to be combined are not in the Cache, write in following way:instructing the tag comparator to search and obtain the search result asto whether a tag identical with the high address of the new data or thecombined data exists in the tag memory: if yes, writing the new data orthe combined data into the Cache line corresponding to the tag; if not,assigning a Cache line to the new data or the combined data, performingCache line replacement according to a preset replacement principle, andwriting the new data or the combined data into the assigned Cache line,or, to the external memory; the tag comparator is configured to: searchthe tag memory to determine whether a tag identical with the highaddress of the new data or the combined data exists according to theinstruction of the Cache controller, and return the search result to theCache controller.
 13. The combiner according to claim 12, wherein, theCache controller being configured to: perform the Cache line replacementaccording to a preset replacement principle in following way: if thereis no data in the assigned Cache line, writing the new data or thecombined data directly into the assigned Cache line, and recording thetag of the Cache line in the tag memory; if there are data in theassigned Cache line, and CRC of the data is correct, then using the newdata or the combined data to replace the data in the Cache line,updating the tag of the Cache line, and writing the updated tag into thetag register; if there are data in the assigned Cache line, and CRC ofthe data is wrong, then proceeding to (a): storing the data in theexternal memory, storing the new data or the combined data into theassigned Cache line, updating the tag of the Cache line, and writing theupdated tag into the tag register; or proceeding to (b): storing the newdata or the combined data into the external memory.
 14. The combineraccording to claim 11, wherein, a Cache line replacement identifier isfurther set in the Cache to indicate whether to perform replacement; theCache controller is further configured to: when performing the Cacheline replacement, if there are data in the assigned Cache line, and theCRC of the data is wrong, then proceed to the (a) when the Cache linereplacement identifier indicates to perform replacement; or else,proceed to the (b).
 15. The combiner according to claim 11, wherein, theHARQ processor is further configured to: when writing the new data orthe combined data of the coded block into the channel decoder, writesecond tag information of the new data or the combined data of the codedblock into the channel decoder, the second tag information of the newdata or the combined data of the same coded block being identical; theCache controller is further configured to: receive the CRC check resultof the new data or the combined data of the coded block and the secondtag information thereof from the channel decoder, and search for acorresponding CRC check result according to the second tag informationof the data that has been stored in the Cache line when performing theCache line replacement.
 16. The combiner according to claim 9, wherein,the HARQ processor is further configured to: receive the CRC checkresult of the coded block from the channel decode and store the CRCcheck result; when receiving the retransmitted data of the coded block,check the stored CRC check result of the coded block, and skip the codedblock when the CRC check result of the coded block indicates that theCRC is correct; obtain the previous data of the coded block and performcombination processing only when the CRC check result of the coded blockindicates that the CRC is wrong.
 17. The method according to claim 5,wherein, before the step of performing the Cache line replacement, themethod further comprises: setting a Cache line replacement identifierfor indicating whether to perform replacement; when performing the Cacheline replacement, if there are data in the assigned Cache line, and theCRC of the data is wrong, then proceeding to the step (a) when the Cacheline replacement identifier indicates to perform replacement; or else,proceeding to the step (b).
 18. The method according to claim 5,wherein, when the HARQ processor writes the new data or the combineddata of the coded block into the channel decoder, the method furthercomprises: writing second tag information of the new data or thecombined data of the coded block to the channel decoder, the second taginformation of the new data or the combined data of the same coded blockbeing identical; the Cache receiving a CRC check result of the new dataor the combined data of the coded block and the second tag informationthereof from the channel decoder, and searching for a corresponding CRCcheck result according to the second tag information of the data thathas been stored in the Cache line when performing the Cache linereplacement.
 19. The combiner according to claim 13, wherein, a Cacheline replacement identifier is further set in the Cache to indicatewhether to perform replacement; the Cache controller is furtherconfigured to: when performing the Cache line replacement, if there aredata in the assigned Cache line, and the CRC of the data is wrong, thenproceed to the (a) when the Cache line replacement identifier indicatesto perform replacement; or else, proceed to the (b).
 20. The combineraccording to claim 13, wherein, the HARQ processor is further configuredto: when writing the new data or the combined data of the coded blockinto the channel decoder, write second tag information of the new dataor the combined data of the coded block into the channel decoder, thesecond tag information of the new data or the combined data of the samecoded block being identical; the Cache controller is further configuredto: receive the CRC check result of the new data or the combined data ofthe coded block and the second tag information thereof from the channeldecoder, and search for a corresponding CRC check result according tothe second tag information of the data that has been stored in the Cacheline when performing the Cache line replacement.